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ISL21400
Data Sheet April 24, 2007 FN8091.1
Programmable Temperature Slope Voltage Reference
The ISL21400 features a precision voltage reference combined with a temperature sensor whose output voltage varies linearly with temperature. The precision 1.20V reference has a very low temperature coefficient (tempco), and its output voltage is scaled by an internal DAC (VREF) to produce a temperature stable output voltage that is programmable from 0V to 1.20V. The output voltage from the temperature sensor (VTS) is summed with VREF to produce a temperature dependent output voltage. The slope of the VTS portion of the output voltage can be programmed to be positive or negative in the range -2.1mV/C to +2.1mV/C. A programmable gain amplifier (PGA) sums the VTS and the VREF voltages and provides gains of 1x, 2x, and 4x to scale the output up to 4.8V and the slope to 8.4mV/C. The VREF and VTS terms are programmable with 8 bits of resolution via an I2C bus and the values are stored in non-volatile registers. The PGA gain is also set via the I2C bus and the value is stored in a non-volatile register. Non-volatile memory storage assures the programmed settings are retained on power-down, eliminating the need for software initialization at device power-up.
Features
* Programmable reference voltage * Programmable temperature slope * Programmable Gain Amplifier * Non-volatile storage of programming registers * I2C serial interface * 2% total accuracy over temperature and VCC range * 200A typical active supply current * Operating temperature range = -40C to +85C * 8 Ld MSOP package * Pb-free plus anneal available (RoHS compliant)
Applications
* RF power amplifier bias compensation * LCD bias compensation * Laser diode bias compensation * Sensor bias and linearization * Data acquisition systems * Variable DAC reference * Amplifier biasing
Temperature Characteristics Curve
3.0 2.5 2.0 VREF (V) TS = 0 1.5 1.0 TS = 0 0.5 0.0 -40 TS = 255 TS = 127 AV = 1 TS = 127 AV = 2
Pinout
ISL21400 (8 LD MSOP) TOP VIEW
A2 A1 A0 VSS VCC VOUT SDA SCL
TS = 255
1 2 3 4
8 7 6 5
-15
10
35
60
85
TEMPERATURE (C)
Ordering Information
PART NUMBER (Note) ISL21400IU8Z ISL21400IU8Z-TK PART MARKING DEW DEW VDD RANGE (V) 2.7 to 5.5 2.7 to 5.5 TEMP RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-free) 8 Ld MSOP (3.0mm), green mtl 8 Ld MSOP (3.0mm), green mtl PKG. DWG. # M8.118 M8.118
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL21400 Pin Description
MSOP 1 2 3 4 5 6 7 8 SYMBOL A2 A1 A0 VSS SCL SDA VOUT VCC DESCRIPTION Hardwire slave address pin for I2C serial bus Hardwire slave address pin for I2C serial bus Hardwire slave address pin for I2C serial bus Ground pin Serial bus clock input Serial bus data input/output Output voltage Device power supply
Block Diagram
VCC
TEMP SENSE
VTS(n) DAC VREF(m) S A VOUT
VREF
DAC GAIN SELECT AV = 1, 2, 4
BIAS SCL COMMUNICATIONS AND REGISTERS SDA
EEPROM 5 BYTES n = 0 to 255 m = 0 to 255 VSS
A0
A1
A2
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ISL21400
Absolute Maximum Ratings
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 6.5V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on VOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to VCC Voltage on All Other Pins . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Thermal Information
Thermal Resistance (Typical) JA (C/ W) 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 130 Moisture Sensitivity for MSOP Package (See Technical Brief TB363) . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL POWER SUPPLY VCC IQ
VCC = 5.5V, TA = +25C to +85C, Unless Otherwise Noted TEST CONDITIONS MIN TYP (Note 2) MAX UNITS
PARAMETER
Supply Voltage Range Supply VCC = 2.7V VCC = 5.5V Standby, SDA = SCL = VCC Standby, SDA = SCL = VCC Nonvolatile write Nonvolatile write
2.7
3.0
5.5
V
200 235
400 500
A A
IQ(NV)
Non-Volatile Supply VCC = 2.7V VCC = 5.5V 500 1.3 2.0 750 1.6 2.6 A mA V
Vpor
Power-on Recall Voltage Minimum VCC at which memory recall occurs VCC Ramp Rate Power-Up Delay VCC above Vpor, time delay to Register recall, and I2C Interface in standby state
VCC Ramp tD
0.2 3
V/ms ms
OUTPUT VOLTAGE PERFORMANCE SPECIFICATIONS GE1 GE2 K Gain Error Gain Error Temperature Sensor Coefficient AV = 2 (Notes 1, 3, 12) AV = 4 (Notes 1, 3, 12) (Notes 1, 8) -1 -1 -2.2 VCC - 0.100 VCC - 0.250 -2.1 -4.2 -8.4 8.2 -2.1 +1 +1 -2.0 GND + 0.100 GND + 0.250 % % mV/C V V mV/C mV/C mV/C V/C per Code 1.0 +1.0 % LSB
Absolute Output Voltage (Swing) Range Unloaded, TA = +25C (Note 3) Absolute Output Voltage (Swing) Range Loaded, IOUT = 500A (Note 3) TS1 TS2 TS3 TS4 Temperature Sensor Slope Temperature Sensor Slope Temperature Sensor Slope AV = 1, n = 255, m = 255 (Notes 1, 6) AV = 2, n = 255, m = 255 (Notes 1, 6) AV = 4, n = 255, m = 255 (Notes 1, 6)
Incremental Temperature Sensor Slope AV = 1, n = 255, m = 0 to 255 (Notes 1, 10) Temperature Slope Non-Linearity DAC Relative Linearity (VCC = 2.7 to 5.5V) n = 255, m = 0 to 255, T = -40C to +85C (Notes 1, 11) VREF and Temp Sense; AV = 1 (Note 13) -1.0
TSNL DNL
0.5
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Analog Specifications
SYMBOL INL VCC = 5.5V, TA = +25C to +85C, Unless Otherwise Noted TEST CONDITIONS VREF and Temp Sense; AV = 1 (Note 13) (Notes 1, 8, 9) AV = 1, n = 255, m = 128, TA = +25C, VCC = 5.5V AV = 2, n = 255, m = 128, TA = +25C, VCC = 5.5V AV = 4, n = 255, m = 128, TA = +25C, VCC = 5.5V AV = 1, n = 255, m = 0, TA = +85C (Note 3) AV = 1, n = 255, m = 128, TA = +85C (Note 3) AV = 1, n = 255, m = 255, TA = +85C (Note 3) AV = 1, n = 255, m = 0, TA = -40C, (Note 3) AV = 1, n = 255, m = 128, TA = -40C, (Note 3) AV = 1, n = 255, m = 255, TA = -40C, (Note 3) 1.189 2.378 4.756 1.315 1.188 1.063 1.052 1.189 1.336 MIN -3.0 1 1.2 2.40 4.80 1.326 1.199 1.074 1.063 1.200 1.325 TYP (Note 2) MAX +3.0 2 1.211 2.422 4.844 1.337 1.210 1.085 1.074 1.211 1.347 UNITS LSB % V V V V V V V V V
PARAMETER DAC Absolute Linearity (VCC = 2.7 to 5.5V)
VOUT(TE) Total Error for VOUT VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 Output Voltage VREF, Gain = 1 Output Voltage VREF, Gain = 2 Output Voltage VREF, Gain = 4 Output Voltage VREF + TS Output Voltage VREF + TS Output Voltage VREF + TS Output Voltage VREF + TS Output Voltage VREF + TS Output Voltage VREF + TS
OUTPUT VOLTAGE DC SPECIFICATIONS PSRR ROUT ISC Power Supply Rejection Ratio Output Impedance (load regulation) Short Circuit, Sourcing Short Circuit, Sinking CL Load Capacitance AV = 1, n = 255, m = 128, (Note 7) Given by ROUT = (VOUT/IOUT), TA = +25C, IOUT = 500A VCC = 5.5V, VOUT = 0V VCC = 5.5V, VOUT = 5.5V Reference output stable for all CL up to specifications 50 60 2 5 6 5 5 9 9 dB mA mA nF
OUTPUT VOLTAGE AC SPECIFICATIONS VN Output Voltage Noise 0.1Hz to 10Hz, AV =1 10Hz to 10kHz, CL = 0, AV = 1 Power On Response Line Ripple Rejection 1% Settling VCC = 5V 100mV, f = 120Hz 90 TBD 500 60 VP-P mVRMS s dB
Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise)
SYMBOL ILI VIL VIH Hysteresis VOL Cpin PARAMETER Input Leakage Input LOW Voltage Input HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage Pin Capacitance IOL = 3mA (Note 3) TEST CONDITIONS VIN = GND to VCC -0.3 0.7 x VCC 0.05 x VCC 0 10 0.4 MIN TYP (Note 2) MAX 1 0.3 x VCC VCC + 0.3 UNITS V V V V V pF
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Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)
SYMBOL fSCL tsp PARAMETER SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid TEST CONDITIONS (Note 3) Any pulse narrower than the max spec is suppressed (Note 3) SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window (Note 3) SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition (Note 3) Measured at the 30% of VCC crossing (Note 3) Measured at the 70% of VCC crossing (Note 3) SCL rising edge to SDA falling edge; both crossing 70% of VCC (Note 3) From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC (Note 3) From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC (Note 3) From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window (Note 3) From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC (Note 3) From SDA rising edge to SCL falling edge; both crossing 70% of VCC (Note 3) From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window (Note 3) From 30% to 70% of VCC (Note 3) From 70% to 30% of VCC (Note 3) Total on-chip and off-chip (Note 4) 1300 MIN TYP (Note 2) MAX 400 50 UNITS kHz ns
tAA
900
ns
tBUF
Time the Bus Must be Free Before the Start of a New Transmission
ns
tLOW tHIGH tSU:STA
Clock LOW Time Clock HIGH Time START Condition Setup Time
1300 600 600
ns ns ns
tHD:STA
START Condition Hold Time
600
ns
tSU:DAT
Input Data Setup Time
100
ns
tHD:DAT
Input Data Hold Time
0
ns
tSU:STO
STOP Condition Setup Time
600
ns
tHD:STO
STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time
1300
ns
tDH
0
ns
tR tF Cb
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL
20 + 0.1 x Cb 20 + 0.1 x Cb 10
250 250 400
ns ns pF
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ISL21400
Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)
SYMBOL Rpu PARAMETER TEST CONDITIONS MIN 1 TYP (Note 2) MAX UNITS k
SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF Off-chip For Cb = 400pF, max is about 2~2.5k For Cb = 40pF, max is about 15~20k Output Leakage Current (SDA only) VOUT = GND to VCC A1, A0, SHDN, SDA, and SCL Input Buffer LOW Voltage A1, A0, SHDN, SDA, and SCL Input Buffer HIGH Voltage SDA Output Buffer LOW Voltage Capacitive Loading of SDA or SCL EEPROM Endurance EEPROM Retention Temperature T +55C IOL = 100A (Note 3), at 3mA sink Total on-chip and off-chip (Note 3)
ILO VIL VIH VOL CL
1 -0.3 VCC x 0.7 0 10 1,000,000 50 12 20 VCC x 0.3 VCC 0.4 400
A V V V pF Cycles Years ms
tWC (Note 14)
Non-Volatile Write Cycle Time
Timing Diagrams
Bus Timing
tF tHIGH tLOW tR tsp tHD:STO
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
Write Cycle Timing
SCL
SDA
8th BIT OF LAST BYTE
ACK tWC STOP CONDITION START CONDITION
NOTES: 1. Equation 1 governs the output voltage and is stated as follows: n ( 2 * m ) - 255 V OUT = A V * V REF * --------- + K ( T - T 0 ) ------------------------------- , n = 0 to 255, m = 0 to 255, K = -2.1mV/C(typ), T0 = +25C 255 255 2. Typical values are for TA = +25C and VCC = 5.5V.
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3. This parameter is not 100% tested. 4. Cb = total capacitance of one bus line in pF. 5. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user. 6. Over the specified temperature range. Temperature slope (TS) is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40C to +85C = +125C. TS1, TS2, TS3 =. V OUT ( Tmin ) - V OUT ( Tmax ) TS = ------------------------------------------------------------------------------Tmin - Tmax 7. Given by PSRR (dB) = 20 * log10 (Vout/VCC) at DC. 8. Test +25C and +85C only. 9. Total error of Equation 1 @ AV =1, K = -2.1mV/C, VREF = 1.20V, m = 255, n = 255 to 0, VCC = 3.0V. V OUT ( measured ) - V OUT ( Equation1 ) V OUT ( TE ) = ------------------------------------------------------------------------------------------------------------ x100% V OUT ( Equation1 ) 10. Over the specified temperature range. Temperature slope (TS) is measured by the box method whereby the change in VOUT is divided by the temperature range. Incremental TS is the temperature slope at m = 255 minus the temperature slope at m = 0 divided by 255 with AV = 1, n = 255 V OUT ( Tmin ) - V OUT ( Tmax ) V OUT ( Tmin ) - V OUT ( Tmax ) TS4 = ------------------------------------------------------------------------------ - ------------------------------------------------------------------------------ / 255 ( Tmin - Tmax ) ( Tmin - Tmax ) m = 255 m = 0 11. Temperature Slope Non- linearity is measured over the specified temperature range. The actual change in output voltage is subtracted from the expected change in output voltage, and then divided by the expected change to normalize before converting to percent. ( T S y ( T ) ) - VOUT TSNL = --------------------------------------------------------- x100%; y = 1, 2, 3 TS y x T 12. For codes n = 8 to 255 13. Guaranteed monotonic 14. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal nonvolatile write cycle. 15. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Typical Performance Curves
3.0 2.5 2.0 VREF (V) TS = 0 1.5 1.0 TS = 0 0.5 0.0 -40 TS = 255 TS = 127 3.5 3.0 -40 AV = 1 TS = 127 AV = 2 6.0 AV = 4 5.5 5.0 VREF (V) 4.5 TS = 127 4.0 TS = 0 TS = 255
TS = 255
-15
10
35
60
85
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 1. VOUT vs TEMPERATURE (AV = 1, 2)
FIGURE 2. VOUT vs TEMPERATURE (AV = 4)
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ISL21400 Typical Performance Curves
1.22 VREF REGISTER = 255d TS REGISTER = 127d
(Continued)
0.40
VREF REGISTER = 255d 0.35 TS REGISTER = 127d 0.30 ICC (mA) 0.25 0.20 0.15 0.10 0.05
+85C
1.21 VREF (V)
+25C
1.20
-40xC -40C
1.19
1.18 2.0
2.5
3.0
3.5
4.0 VCC (V)
4.5
5.0
5.5
6.0
0
2
3
4 VCC (V)
5
6
7
FIGURE 3. VOUT vs VCC (VCC = +2.7V to +5.5V)
FIGURE 4. SUPPLY VOLTAGE vs SUPPLY CURRENT
NO LOAD AV = 1 100V/DIV (VOUT x 1000)
NO LOAD AV = 4 50V/DIV (VOUT x 1000)
FIGURE 5. VOUT VOLTAGE NOISE (AV = 1, NO LOAD)
FIGURE 6. VOUT VOLTAGE NOISE (AV = 4, NO LOAD)
1.22
CH1 = VCC
1.21 VREF (V)
CH2 = VOUT
1.20
1.19 VREF REGISTER = 255d TS REGISTER = 127d 1.18 -40 -15 10 35 60 85
TEMPERATURE (C)
FIGURE 7. ACCURACY vs TEMPERATURE (-40C TO +85C)
FIGURE 8. POWER ON
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ISL21400 Typical Performance Curves
3 2 1 INL IN LSB 0 AT +25C -1 -2 -3 DNL IN LSB
(Continued)
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 CODE -1.0 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 CODE AT +25C
FIGURE 9. INL, VREF AND TEMP SLOPE DAC
FIGURE 10. DNL, VREF AND TEMP SLOPE DAC
1.4 1.2 1.0 VREF (V)
AT +25C TS REGISTER = 127d
1.40 1.35 1.30 VREF (V) 1.25 +85C 1.20 1.15 1.10
VREF REGISTER = 255d
0.8 0.6 0.4
-40C
0.2 0.0 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 VREF REGISTER CODE (m)
1.05 1.00 0 15 30 45 60 75 90 105 120 135 15 0 165 180 195 210 225 240 255 TS REGISTER CODE (n)
FIGURE 11. VOUT vs VREF CODE (m)
FIGURE 12. VOUT vs TEMP SENSE CODE (n), TA = -40C AND +85C
1.209 1.208 1.207 1.206 VREF (V) 1.205 1.204 1.203 1.202 1.201 1.2 -1 -0.5 0 IOUT (mA) 0.5 1 VREF REGISTER = 255d TS REGISTER = 127d AT +25C
FIGURE 13. VOUT vs IOUT (1mA)
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ISL21400 Pin Descriptions
VOUT
Programmable voltage output pin. Absolute voltage is determined by device temperature and Equation 1. Drive capability is limited to 500A output current and 5000pF output capacitance.
Reference Sections
Referring to the Block Diagram on page 2, the VREF and Temperature Sense (VTS) outputs are summed together () and then passed through the output gain stage (A). The voltage output is programmable and is determined by the Equation 1:
n ( 2 * m ) - 255 V OUT = A V * V REF * --------- + V TS ------------------------------- 255 255 (EQ. 1)
A2, A1, A0
Hardware slave address pins that can be used to provide several ISL21400 with a unique physical address to allow for multiple devices off one I2C bus.
where * AV = 1, 2, 4 * VREF = 1.200 (not temperature dependent) * 0 n 255 (setting contained in Register 0, VREF) * VTS = K(T - T0) * K = dVTS/ dT = -2.1mV/C * T = device temperature * T0 = +25C * 0 m 255 (setting contained in Register 1, TS) See "Applications Information" on page 14 for ways to use Equation 1 and methods for output voltage calculations.
GND
This is the circuit ground pin. It is common for the VOUT and control signal inputs.
SDA
Serial Data Input/Output. Bidirectional pin used for serial data transfer. As an output, it is open drain and may be wire-ored with any number of open drain or open collector outputs. A pullup resistor is required and the value is dependent on the speed of the serial data bus and the number of outputs tied together.
SCL
Serial Clock Input. Accepts a clock signal for clocking serial data into and out of the device. The SCL line requires a pull-up resistor whose value is dependent on the speed of the serial clock bus and the number of inputs tied together.
DACs Section
The ISL21400 contains two 8-bit DACs whose registers can be programmed via the I2C serial bus. The DAC registers are non-volatile such that the values are restored during the VCC power-up cycle of the device. One DAC (VREF) is dedicated to scale the bandgap voltage reference (Temperature invariant) and the other DAC (VTS) is dedicated to scale the Temperature Sensor. Both of these DACs can determine the output voltage as defined by Equation 1 (See "Register Descriptions" on page 11.).
VCC
Positive Power Supply. Connect to a voltage supply in the range of 2.7V < VCC < 5.5V, with minimum noise and ripple. For best performance, bypass with a 0.1F capacitor to ground. If the AV gain is set to 4 and VOUT approaches 5.0V, then VCC must be set to >5.2V for best output performance.
Output Gain Amplifier Section
Functional Description
Functional Overview
Refer to the Functional Block Diagram on page 2. The ISL21400 provides a programmable output voltage which combines both a temperature independent term and a temperature dependent term. The temperature independent term uses a bandgap voltage reference, and the temperature dependent term uses a Proportional To Absolute Temperature (PTAT) reference, or Temperature Sensor. Each voltage source is scalable using two DACs via the I2C serial bus. The resulting output voltage can vary from 0V to over 5V and has a variable, programmable Temperature Slope (TS).
The ISL21400 contains an output gain amplifier (A) that is programmed via the I2C serial bus. The gain amplifier is the last stage before the output and therefore controls the overall gain for the device. The gain can be programmed for 1x, 2x, or 4x amplification. This gain factor is used to program the output voltage as determined by Equation 1 (See "Register Descriptions" on page 11.). There are 5 registers in the ISL21400 device, all nonvolatile (see Table 2). All registers are accessible for reading or writing through the I2C serial bus.
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Register Descriptions
TABLE 1. ISL21400 REGISTER BIT MAP Addr 0 1 2 3 4 D7 (MSB) VREF7 TS7 D7 D7 D7 D6 VREF6 TS6 D6 D6 D6 D5 VREF5 TS5 D5 D5 D5 D4 VREF4 TS4 D4 D4 D4 D3 VREF3 TS3 D3 D3 D3 D2 VREF2 TS2 D2 D2 D2 D1 VREF1 TS1 GAIN1 D1 D1 D0 (LSB) VREF0 TS0 GAIN0 D0 D0
TABLE 2. REGISTER DESCRIPTIONS REG 0 1 2 3 4 NONVOLATILE Y Y Y Y Y DESCRIPTION Reference setting Temperature Sensor setting Gain and storage Storage Storage
and the resulting output gain. Note that two states produce the same gain (Gain 1:0 set to 01b and 10b) of x2. The other 6-bits in the register can be used for general purpose memory (nonvolatile) or left alone.
Registers 3 and 4: general purpose data (nonvolatile)
These two registers are one byte each and can be used for general purpose nonvolatile memory.
Register 0: Bandgap Reference Gain (Nonvolatile)
Register 0 sets the output voltage of the bandgap reference (VREF). Referring to Equation 1, the number "n" is the setting from Register 0 as follows:
n V REF * --------- , for n = 0 to 255 255
I2C Serial Interface
The ISL21400 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL21400 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
This term of Equation 1 can vary from 0V to 1.20V.
Register 1: Temperature Slope Gain (Nonvolatile)
Register 1 sets the Temperature Slope (TS) of the temperature sensor. Referring to Equation 1, the number "m" is the setting from Register 1 as follows:
( 2 * m ) - 255 V TS ------------------------------255
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 10). On power-up of the ISL21400 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL21400 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 10). A START condition is ignored during the powerup sequence and during non-volatile write cycles for the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 10) A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. A STOP condition at the end of a write operation to a non-volatile byte initiates an internal
VTS is the temperature dependent term and varies from +136mV at -40C to -126mV at +85C. The other term varies from -1 to +1 and scales the temperature term before adding to the VREF portion.
Register 2: Device Gain and Storage (nonvolatile)
TABLE 3. REGISTER 2 OUTPUT GAIN (NONVOLATILE): OUTPUT GAIN GAIN1 0 0 1 1 GAIN0 0 1 0 1 OUTPUT GAIN, AV x1 x2 x2 x4
Register 2 contains 2 bits (2 LSB's) which control the output gain of the device. Table 3 shows the state of these two bits 11
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ISL21400
non-volatile write cycle. The device enters its standby state when the internal, non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 11). The ISL21400 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL21400 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101 A2 A1 A0 as the seven MSBs. The A2 A1 A0 bits must correspond to the logic levels at those pins of the ISL21400 device. The LSB in the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (See Table 4).
Read Operation
A Current Address Read operation is shown in Figure 13. It consists of a minimum 2 bytes: a START followed by the ID byte from the master with the R/W bit set to 1, then an ACK followed by the data byte or bytes sent by the slave. The master terminates the Read operation by not responding with an ACK and then issuing a STOP condition. This operation is useful if the master knows the current address and desires to read one or more data bytes. A Random Address Read operation consists of a three byte "dummy write" instruction followed by a Current Address Read operation (See Figure 14). The master initiates the operation issuing the following sequence: a START, the identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL21400 responds with an ACK. The ISL21400 then transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the Read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 13). The Data Bytes are from the registers indicated by an internal pointer. This pointer initial's value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. Address 04h is the last valid data byte, higher addresses are not available. Data from addresses higher than memory location 04h will be invalid.
Write Operation
TABLE 4. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 A2 A1 A0 R/W (LSB)
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL21400 responds with an ACK. The master will then send a STOP and at this time the device begins its internal non-volatile write cycle. During this time, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL21400 enters its standby state (see Figure 12). STOP conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated ACK signal. If a STOP byte is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the ISL21400 resets itself without performing the write. The contents of the array are not affected.
Data Protection
A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection for the registers. A STOP condition also acts as a protection for non-volatile memory. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. The presence of the STOP condition after the rest of the bits are received then triggers the non-volatile write.
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FN8091.1 April 24, 2007
ISL21400
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 14. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER
1
8
9 HIGH
SDA OUTPUT FROM RECEIVER START
HIGH
ACK
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T IDENTIFICATION BYTE WITH R/W = 0 S T O P
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL21400
01
0 1 A2 A1 A0 0
0000
0
A C K
A C K
A C K
FIGURE 16. BYTE WRITE SEQUENCE
READ SIGNALS FROM THE MASTER S T A R T IDENTIFICATION BYTE WITH R/W = 1 A C K A C K S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
0 1 0 1 A2 A1 A0 1
A C K
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 17. ADDRESS READ SEQUENCE
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FN8091.1 April 24, 2007
ISL21400
SIGNALS FROM THE MASTER
S T A IDENTIFICATION R BYTE WITH R/W = 0 T
0 1 0 1 A AA0
ADDRESS BYTE
S T A R IDENTIFICATION T BYTE WITH R/W = 1
0 1 0 1 AAA1
A C K
A C K
S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
00000
A C K
A C K
A C K
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 18. RANDOM ADDRESS READ SEQUENCE
Applications Information
Power-Up Considerations
The ISL21400 has on-chip EEPROM memory storage for the DAC and gain settings of the device. These settings must be recalled correctly on power-up for proper operation. Normally there are no issues with recall, although it is always best to provide a smooth, glitch-free power-up waveform on VCC. Adding a small 0.1F capacitor at the device VCC will help with power-up as well as VOUT load changes.
DC OUTPUT CONTROL DISCUSSION The reference term yields Equation 2 for Reference Output:
V OUT (DC) = A * V REF * A REF V (EQ. 2)
Noise Performance
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 90VP-P. The noise measurement is made with a bandpass filter made of a 1 pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Load capacitance up to 5000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21400 is not designed to drive heavily capacitive loads. For high impedance loads, an R-C network can be added to filter high frequency noise and preserve DC control.
Note that the DC term is dependent on the 1.20V reference voltage, which is constant, the overall gain, AV, and the Reference gain, AREF. Since the product AV * AREF ranges from 0 to 4, the total reference DC output can range from 0.0V to 4.8V. In order to get the 4.8V output, VCC must be greater than 4.8V by the output dropout plus any overhead for output loading (the specification for VOUT = 5.0V is listed with VCC = 5.5V). The Resolution of VOUT(DC) control changes with AV, so that with a 4.80V full scale output (AV = 4), the resolution is 4.80/255 or 18.8mV/bit. With AV = 1, the resolution is 4.7mV/bit. TEMP SENSE CONTROL DISCUSSION Equation 2 yields this expression, Equation 3, for Temp Slope:
V OUT ( TS ) = A V * V TS * A TS (EQ. 3)
Output Voltage Programming Considerations
Setting and controlling the output voltage of the ISL21400 can be done easily by breaking down the components into temperature variant and invariant, and setting them separately. Let's use Equation 1 to derive separate Reference Output and Output Temp Slope equations:
( 2 * m ) - 255 n V OUT = A V * V REF * --------- + A V * V * ---------------------------------- TS 255 255 = { A V * V REF * A REF } + { A V * V
TS
Since VTS = K(T - T0), the slope term is dependent on the base temp slope of the device, K (-2.1mV/C), and the gain terms AV and ATS. This gives a formula (Equation 4) for the portion of VOUT at a specific temperature:
V OUT ( TS ) = A V * K * A TS * ( T - T 0 ) (EQ. 4)
* A TS }""
Reference Term + Temp Slope Term
The product AV*ATS ranges from -4 to 4, so the Temperature Slope can range from -8.4 to +8.4mV/C, which is independent of the output DC voltage. The resolution of Slope control is determined by this range (8.4mV/C) and the gain terms, and will vary from 65.8V/C/bit (AV = 4) down to 16.2V/C/bit (AV = 1). At T = T0 = +25C, VOUT(TS) = 0, no changes in ATS will cause a change in VOUT, and VOUT will only vary with the VOUT(DC) control. As temperature increases or decreases, from T = +25C, VOUT will then change according to the programmed Temp Slope.
The first term controls the output DC value, and the second term controls the Temp slope, where
nA REF = --------- (ranges from 0 to 1) 255 ( 2 * m ) - 255 A TS = ---------------------------------- 255 (ranges from -1 to +1)
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ISL21400
In many cases a form of Equation 4 is needed which yields a VOUT change with respect to temperature. By rearranging, we get:
V OUT ( TS ) V OUT ( T ) = ---------------------------- = A V * K * A TS ,(in mV/C ) ( T - T0 ) (EQ. 5)
VOUT parameters, the system characteristics can be recorded. For the example below, let's determine the voltage output, VOUT(DC) at +25C, and also the change due to temperature variation (ppm) from +25C to +85C. Equations 2 and 5 will be used to calculate the answers. Given, the contents of the registers: AV = 1 n = 178 decimal m = 74 decimal Using Equation 2:
V OUT ( DC ) = ( A V * V REF * A REF ) 178 = 1 * 1.20 * --------- 255 = 0.8376V
EXAMPLE 1: PROGRAMMED TEMPERATURE COMPENSATION EXAMPLE The ISL21400 can easily compensate for known temperature drift by programming the device for the initial VOUT setting and Tempco using standard equations and some simple steps. The accuracy of the final programmed output will be limited to the data sheet specs (typically 1% accuracy for VOUT and Slope). In this example, an N-Channel MOSFET gate has a -2.8mV/C Tempco from -10C to +85C. A constant bias drain current is desired, with a target Vgs range derived from the data sheet of 2.5V to 3.5V at +25C. Offset Setting: Using Equation 2 and targeting VOUT = 3.0VDC:,
V OUT ( DC ) = ( A V * V REF * A REF ) = 3.00V V REF = 1.20V A V * A REF = 2.50
Using Equation 5:
V OUT ( T ) = ( A V * K * A TS ) mV C ( 2 * 74 ) - 255 = 1 * - 2.1 * ----------------------------------255 = 0.8812mV C
Also, to solve for overall temp slope of the output:
6 0.8812mV C --------------------------------------- * 10 = 1010ppm C 872.5mV
Note that AREF varies from 0 to 1, so to get 2.40, AV = 4.
2.50 n A ( REF ) = ---------- = 0.625 = --------4 255 n = 159 decimal = 9F hex
Note that Equation 1 can be used directly to solve for output voltage at a given temperature, in this case +85C:
n ( 2 * m ) - 255 V OUT = A V * V REF * --------- + K ( T - T 0 ) ------------------------------- 255 255 1 V OUT ( +85C ) = = * 1.20 * --------- + ( - 0.0021 ) ( 85 - 25 ) --------------------------------- 255 255 = 0.8905V 178 ( 2 * 74 ) - 255
Temperature Slope Setting: Using Equation 5, which can solve for Slope directly:
V OUT ( T ) = A V * K * A TS = - 2.8mV C - 2.8 A TS = ------------------4 * - 2.1 ( 2 * m ) - 255 A TS = 0.333 = ---------------------------------255 m = 170 decimal = A9 hex
Typical Applications Circuits
LDMOS RF Power Amplifier (RFPA). The ISL21400 is used to set the gate bias for the LDMOS transistor in a single stage of an RFPA. Normally this is done with a DAC or digital potentiometer with some discrete temperature compensation circuitry. The ISL21400 simplifies this control and allows a full range of DC bias and tempco control. A typical circuit can be calibrated for correct bias at room temperature (+25C) on power-up using a microcontroller or direct I2C control. The temperature of the unit can then be increased to the highest operating range, and the Temperature Slope setting can then be adjusted to bring the amplifier back to correct bias. Since the Temp Slope setting has a negligible effect on the room temperature setting, the amplifier will be biased correctly over the operating temperature of the unit.
The ISL21400 device can be programmed with these calculated parameters and perform temperature compensation or direct control in the target circuit. If parameters change for some reason, then the device can be reprogrammed with new values and the circuit retested. EXAMPLE 2. CALCULATING THE VOUT TEMPERATURE SLOPE In some applications, it may be desirable to calculate what the output voltage and temp slope are, given the programmed register settings. Such an application could be a closed loop system with internal calibration procedure. By reading the registers of the ISL21400, then calculating the
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FN8091.1 April 24, 2007
ISL21400
+28V U2 1 IN OUT 3
2 GND +5V REGULATOR
+28V
I2C BUS
5 6 1 2 3
SCL SDA A0 A1 A2 A2
VCC VOUT
8 7 R1 1k R2 100 C1 100pF RF OUTPUT L1
GND 4
ISL21400
C2 RF INPUT
Q1 LDMOS
FIGURE 19. LDMOS RFPA BIAS CONTROL
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FN8091.1 April 24, 2007
ISL21400 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 4.75 0.40 8 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 2 01/03
MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 0.187 0.016 8 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 0.199 0.028
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.026 BSC
0.65 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1 0
SIDE VIEW
15o 6o
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN8091.1 April 24, 2007

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